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1 ? fn9247.0 isl8102 two-phase buck pwm controller with high current integrated mosfet drivers the isl8102 is a two-phase pwm control ic with integrated mosfet drivers. it provides a precision voltage regulation system for multiple applications including, but not limited to, high current low voltage point-of-load converters, embedded applications and other general purpose low voltage medium to high current applications. the integration of power mosfet drivers into the controller ic marks a departure from the separate pwm controller and driver configuration of previous multi-phase product families. by reducing the number of external parts, this integration allows for a cost and space saving power management solution. output voltage can be programmed using the on-chip dac or an external precision reference. a two bit code programs the dac reference to one of 4 possible values (0.6v, 0.9v, 1.2v and 1.5v). a unity gain, di fferential amplifier is provided for remote voltage sensing, compensating for any potential difference between remote and local grounds. the output voltage can also be offset through the use of single external resistor. an optional droop function is also implemented and can be disabled for applications having less stringent output voltage variation requirements or experiencing less severe step loads. a unique feature of the isl8102 is the combined use of both dcr and r ds(on) current sensing. load line voltage positioning and overcurrent protection are accomplished through continuous inductor dcr current sensing, while r ds(on) current sensing is used for accurate channel-current balance. using both me thods of current sampling utilizes the best advantages of each technique. protection features of this c ontroller ic include a set of sophisticated overvoltage and overcurrent protection. overvoltage results in the converter turning the lower mosfets on to clamp the rising output voltage and protect the load. an ovp output is also provided to drive an optional crowbar device. the overcurrent protection level is set through a single external resistor. other protection features include protection against an open circuit on the remote sensing inputs. combined, these features provide advanced protection for the output load. features ? integrated multi-ph ase power conversion - 1 or 2 phase operation ? precision output voltage regulation - differential remote voltage sensing - 0.8% system accuracy over temperature (for ref=0.6v and 0.9v) - 0.5% system accuracy over temperature (for ref=1.2v and 1.5v) - usable for output voltages not exceeding 2.3v - adjustable reference-voltage offset ? precision channel current sharing - uses loss-less r ds(on) current sampling ? optional load line (droop) programming - uses loss-less inductor dcr current sampling ? variable gate-drive bias - 5v to 12v ? internal or external reference voltage setting - on-chip adjustable fixed dac reference voltage with 2-bit logic input selects from four fixed reference voltages (0.6v, 0.9v, 1.2v, 1.5v) - reference can be changed dynamically - can use an external voltage reference ? overcurrent protection ? multi-tiered overvoltage protection - ovp pin to drive optional crowbar device ? selectable operation frequency up to 1.5mhz per phase ? digital soft-start ? capable of start-up in a pre-biased load ? pb-free plus anneal available (rohs compliant) applications ? high current ddr/chipset core voltage regulators ? high current, low voltage dc/dc converters ? high current, low voltage fpga/asic dc/dc converters ordering information part number* part marking temperature (c) package pkg. dwg. # isl8102crz (note) isl8102crz 0 to 70 32 ld 5x5 qfn (pb-free) l32.5x5 ISL8102IRZ (note) ISL8102IRZ -40 to 85 32 ld 5x5 qfn (pb-free) l32.5x5 isl8102eval1 evaluation platform * add ?-t? suffix for tape and reel. note: intersil pb-free plus anneal products employ special pb-f ree material sets; molding com pounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet october 19, 2005 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn9247.0 october 19, 2005 pinout isl8102 (qfn) top view rgnd ref1 ref0 pgood lgate1 boot1 2ph fs isen1 ugate1 phase1 ovp enll boot2 phase2 vsen ocset icomp isum iref lgate2 pvcc isen2 ugate2 dac ref ofst vcc comp fb vdiff droop 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10111213141516 33 gnd isl8102
3 fn9247.0 october 19, 2005 block diagram dac dac ref1 ref0 e/a ref fb offset ofst comp isum iref icomp isen amp oc ocset rgnd vsen vdiff 100a +150mv ovp x 0.82 ovp uvp isen1 isen2 channel current sense 1 n pwm1 pwm2 channel current balance through shoot- protection boot1 ugate1 phase1 lgate1 pvcc logic control gate through shoot- protection boot2 ugate2 phase2 lgate2 logic control gate clock and generator sawtooth soft-start and fault logic phase 2 detect vcc reset power-on 0.66v enll fs pgood gnd 0.2v +1v droop ovp 2ph x1 x1 isl8102
4 fn9247.0 october 19, 2005 typical application - isl8102 pgood vdiff fb comp vcc isen1 isl8102 ref1 fs ofst ref +12v +12v phase1 ugate1 boot1 lgate1 isen2 phase2 ugate2 boot2 lgate2 isum icomp iref load vsen rgnd ocset ref0 +5v pvcc enll +12v gnd ovp 2ph dac droop isl8102
5 fn9247.0 october 19, 2005 absolute m aximum ratings supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v supply voltage, pvcc . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +15v absolute boot voltage, v boot . . . . . . . . gnd - 0.3v to gnd + 36v phase voltage, v phase . . . . . . . . gnd - 0.3v to 15v (pvcc = 12) gnd - 8v (<400ns, 20j) to 24v (<200ns, v boot-phase = 12v) upper gate voltage, v ugate . . . . v phase - 0.3v to v boot + 0.3v v phase - 3.5v (<100ns pulse width, 2j) to v boot + 0.3v lower gate voltage, v lgate . . . . . . . . gnd - 0.3v to pvcc + 0.3v gnd - 5v (<100ns pulse width, 2j) to pvcc+ 0.3v input, output, or i/o voltage . . . . . . . . . gnd - 0.3v to vcc + 0.3v esd classification . . . . . . . . . . . . . . . . . . . . . . . class i jedec std recommended operating conditions vcc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% pvcc supply voltage . . . . . . . . . . . . . . . . . . . . . . . +5v to 12v 5% ambient temperature (isl8102cr, isl8102crz) . . . . 0c to 70c ambient temperature (isl8102ir, ISL8102IRZ) . . . .-40c to 85c thermal information thermal resistance ja (c/w) jc (c/w) qfn package (notes 1, 2) . . . . . . . . . . 35 5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c caution: stress above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress onl y rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions, unless otherwise specified. parameter test conditions min typ max units bias supply and internal oscillator input bias supply current i vcc ; enll = high - 15 20 ma gate drive bias current i pvcc ; enll = high, all gate outputs open, fsw = 250khz -1.53.0ma vcc por (power-on reset) threshold vcc rising 4.25 4.38 4.50 v vcc falling 3.75 3.88 4.00 v pvcc por (power-on reset) threshold pvcc rising 4.25 4.38 4.50 v pvcc falling 3.75 3.88 4.00 v oscillator ramp amplitude (note 3) v pp -1.50-v maximum duty cycle (note 3) - 66.6 - % control thresholds enll rising threshold -0.66-v enll hysteresis - 100 - mv comp shutdown threshold comp falling 0.25 0.35 0.5 v reference and dac system accuracy (dac = 0.6v, 0.9v) droop connected to iref -0.8 - 0.8 % system accuracy (dac = 1.2v, 1.50v) droop connected to iref -0.5 - 0.5 % dac input low voltage (ref0, ref1) - - 0.4 v dac input high voltage (ref0, ref1) 0.8 - - v external reference (note 3) 0.6 - 1.75 v ofs sink current accuracy (negative offset) r ofs = 30k ? from ofs to vcc 47.5 50.0 52.5 a ofs source current accuracy (positive offset) r ofs = 10k ? from ofs to gnd 47.5 50.0 52.5 a isl8102
6 fn9247.0 october 19, 2005 error amplifier dc gain (note 3) r l = 10k to ground - 96 - db gain-bandwidth product (note 3) c l = 100pf, r l = 10k to ground - 20 - mhz slew rate (note 3) c l = 100pf, load = 400 a-8-v/ s maximum output voltage load = 1ma 3.90 4.20 - v minimum output voltage load = -1ma - 0.85 1.0 v remote sense differential amplifier input bias current (vsen) (vsen = 1.5v) 49 55 60 a bandwidth (note 3) -20-mhz slew rate (note 3) -8-v/ s overcurrent protection ocset trip current 93 100 107 a ocset accuracy oc comparator offset (ocset and isum difference) -5 0 5 mv icomp offset isen amplifier offset -5 0 5 mv protection undervoltage threshold vsen falling 80 82 84 %dac undervoltage hysteresis vsen rising - 3 - %dac overvoltage threshold while ic disabled 1.62 1.67 1.72 v overvoltage threshold vsen rising dac + 125mv dac + 150mv dac + 175mv v overvoltage hysteresis vsen falling - 50 - mv open sense-line protection thres hold iref rising and falling vdiff + 0.9v vdiff + 1v vdiff + 1.1v v ovp output high drive voltage i ovp = 15ma, vcc = 5v 2.2 3.4 - v switching time ugate rise time (note 3) t rugate; v pvcc = 12v, 3nf load, 10% to 90% - 26 - ns lgate rise time (note 3) t rlgate; v pvcc = 12v, 3nf load, 10% to 90% - 18 - ns ugate fall time (note 3) t fugate; v pvcc = 12v, 3nf load, 90% to 10% - 18 - ns lgate fall time (note 3) t flgate; v pvcc = 12v, 3nf load, 90% to 10% - 12 - ns ugate turn-on non-overlap (note 3) t pdhugate ; v pvcc = 12v, 3nf load, adaptive - 10 - ns lgate turn-on non-overlap (note 3) t pdhlgate ; v pvcc = 12v, 3nf load, adaptive - 10 - ns gate drive resistance (note 3) upper drive source resistance v pvcc = 12v, 150ma source current 1.25 2.0 3.0 ? upper drive sink resistance v pvcc = 12v, 150ma sink current 0.9 1.6 3.0 ? lower drive source resistance v pvcc = 12v, 150ma source current 0.85 1.4 2.2 ? lower drive sink resistance v pvcc = 12v, 150ma sink current 0.60 0.94 1.35 ? over temperature shutdown thermal shutdown setpoint (note 3) - 160 - c thermal recovery setpoint (note 3) - 100 - c note: 3. parameter magnitude guaranteed by design. not 100% tested. electrical specifications recommended operating conditions, unless otherwise specified. (continued) parameter test conditions min typ max units isl8102
7 fn9247.0 october 19, 2005 timing diagram simplified power system diagram functional pin description vcc (pin 3) bias supply for the ic?s small-signal circuitry. connect this pin to a +5v supply and locally decouple using a quality 1.0 f ceramic capacitor. pvcc (pin 15) power supply pin for the mosfet drive. this pin can be connected to any voltage from +5v to +12v, depending on the desired mosfet gate drive level. gnd (pin 33) bias and reference ground for the ic. enll (pin 20) this pin is a threshold sensit ive (approximately 0.66v) enable input for the controller. held low, this pin disables controller operation. pulled high, the pin enables the controller for operation. fs (pin 29) a resistor, placed from fs to ground, will set the switching frequency. refer to equation 33 and figure 24 for proper resistor calculation. 2ph (pin 31) this pin is used to choose between single or two phase operation. tying this pin to vcc allows for 2-phase operation. tying the 2ph pin to gnd causes the controller to operate in a single phase mode. ref0 and ref1 (pins 30, 21) these pins make up the 2-bit input that selects the fixed dac reference voltage. these pins respond to ttl logic thresholds. the isl8102 decodes these inputs to establish ugate lgate t flgate t pdhugate t rugate t fugate t pdhlgate t rlgate channel1 +5v in v out q1 q2 isl8102 dac channel2 q3 q4 +12v in enll pgood 2 ref0,ref1 ovp isl8102
8 fn9247.0 october 19, 2005 one of four fixed reference voltages; see ?table 1? for correspondence between ref0 and ref1 inputs and reference voltage settings. these pins are internally pulled high, to approximately 1.2v, by 40 a (typically) internal current sources; the internal pull- up current decreases to 0 as the ref0 and ref1 voltages approach the internal pull-up voltage. both ref0 and ref1 pins are compatible with external pull-up voltages not exceeding the ic?s bias voltage (vcc). vsen and rgnd (pins 8, 7) vsen and rgnd are inputs to the precision differential remote-sense amplifier and shou ld be connected to the sense pins of the remote load. icomp, isum, and iref (pins 10, 12, 13) isum, iref, and icomp are the dcr current sense amplifier?s negative input, positive input, and output respectively. for accurate d cr current sensing, connect a resistor from each channel?s phase node to isum and connect iref to the summing point of the output inductors, roughly vout. a parallel r-c feedback circuit connected between isum and icomp will then create a voltage from iref to icomp proportional to the voltage drop across the inductor dcr. this voltage is referred to as the droop voltage and is added to the differential remote-sense amplifier?s output an optional 0.001-0.01 f ceramic capacitor can be placed from the iref pin to the isum pin to help reduce common mode noise that might be in troduced by the layout. droop (pin 11) this pin enables or disables droop. tie this pin to the icomp pin to enable droop. to disable droop, tie this pin to the iref pin. vdiff (pin 6) vdiff is the output of the diff erential remote-sense amplifier. the voltage on this pin is equal to the difference between vsen and rgnd added to the difference between iref and icomp. vdiff therefore represents the vout voltage plus the droop voltage. fb and comp (pins 5, 4) the internal error amplifier? s inverting input and output respectively. fb is connected to vdiff through an external r or r-c network depending on the desired type of compensation (type ii or iii). comp is tied back to fb through an external r-c network to compensate the regulator. dac (pin 32) the dac pin is the direct output of the internal dac. this pin is connected to ref pin using 1-5k ? resistor, this pin can be left open if an external reference is used. ref (pin 1) the ref input pin is the positive input of the error amplifier. this pin can be connected to the dac pin using a resistor (1-5k ? ) when the internal dac voltage is used as the reference voltage. when an external voltage reference is used, it must be connected directly to the ref pin, while the dac pin is left unconnected. the output voltage will be regulated to the voltage at the ref pin unless th is voltage is greater than the voltage at the dac pin. if an exte rnal reference is used at this pin, its magnitude cannot exceed 1.75v. a capacitor is used between the ref pin and ground to smooth the dac voltage during soft-start. ofst (pin 2) the ofst pin provides a means to program a dc current for generating an offset voltage ac ross the resistor between fb and vdiff. the offset current is generated via an external resistor and precision internal voltage references. the polarity of the offset is selected by connecting the resistor to gnd or vcc. for no offset, the ofst pin should be left unconnected. ocset (pin 9) this is the overcurrent set pin. placing a resistor from ocset to icomp, allows a 100 a current to flow out of this pin, producing a voltage reference. in ternal circuitry compares the voltage at ocset to the voltage at isum, and if isum ever exceeds ocset, the overcurr ent protection activates. isen1, isen2 (pins 26, 16) these pins are used for balancing the channel currents by sensing the current through each channel?s lower mosfet when it is conducting. connect a resistor between the isen1 and isen2 pins and their respective phase node. this resistor sets a current proporti onal to the current in the lower mosfet during its conduction interval. ugate1 and ugate2 (pins 25, 17) connect these pins to the upper mosfets? gates. these pins are used to control the upper mosfets and are monitored for shoot-through prevention purposes. maximum individual chan nel duty cycle is limited to 66%. boot1 and boot2 (pins 24,18) these pins provide the bias voltage for the upper mosfets? drives. connect these pins to appropriately-chosen external bootstrap capacitors. internal bootstrap diodes connected to the pvcc pins provide the nec essary bootstrap charge. phase1 and phase2 (pins 23, 19) connect these pins to the sources of the upper mosfets. these pins are the return path for the upper mosfets? drives. lgate1 and lgate2 (pins 27, 14) these pins are used to control the lower mosfets and are monitored for shoot-through prevention purposes. connect these pins to the lower mosfets? gates. do not use isl8102
9 fn9247.0 october 19, 2005 external series gate resistors as this might lead to shoot- through. pgood (pin 28) pgood is used as an indication of the end of soft-start. it is an open-drain logic output that is low impedance until the soft- start is completed and v out is equal to the vid setting. once in normal operation pgood i ndicates whether the output voltage is within specified overvoltage and undervoltage limits. if the output voltage exceeds these limits or a reset event occurs (such as an overcurr ent event), pgood becomes high impedance again. the potential at this pin should not exceed that of the potential at vcc pin by more than a typical forward diode drop at any time ovp (pin 22) overvoltage protection pin. this pin pulls to vcc when an overvoltage condition is detect ed. connect this pin to the gate of an scr or mosfet tied across v in and ground to prevent damage to a load device. operation multi-phase power conversion modern low voltage dc/dc conver ter load current profiles have changed to the point that the advantages of multi- phase power conversion are impossible to ignore. the technical challenges associated with producing a single- phase converter that is both cost-effective and thermally viable have forced a change to the cost-saving approach of multi-phase. the isl8102 controller helps simplify implementation by integrating vital functions and requiring minimal external components. the block diagram on page 2 provides a top level view of multi-phase power conversion using the isl8102 controller. interleaving the switching of each channel in an isl8102-based converter is timed to be symme trically out of phase with the other channel. as a result, the two-phase converter has a combined ripple frequency twice the frequency of one of its phases. in addition, the peak -to-peak amplitude of the combined inductor currents is proportionately reduced (equations 1 and 2). increased ripple frequency and lower ripple amplitude generally translate to lower per-channel inductance and lower total output capacitance for a given set of performance specifications. figure 1 illustrates the additive effect on output ripple frequency. the two channel currents (i l1 and i l2 ), combine to form the ac ripple current and the dc load current. the ripple component has two times the ripple frequency of each individual channel current. to understand the reduction of ripple current amplitude in the multi-phase circuit, examine the equation representing an individual channel peak-to-peak inductor current. in equation 1, v in and v out are the input and output voltages respectively, l is the single-channel inductor value, and f sw is the switching frequency. the output capacitors conduct the ripple component of the inductor current. in the case of multi-phase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. compare equation 1 to the expression for the peak-to-peak current after the summation of n symmetrically phase-shifted inductor currents in equation 2. peak-to-peak ripple current decreases by an amount proportional to the number of channels. output voltage ripple is a function of capacitance, capacitor equivalent series resistance (esr), and inductor ripple current. reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors. another benefit of interleaving is to reduce input ripple current. input capacitance is determined in part by the maximum input ripple current. multi-phase topologies can improve overall system cost and size by lowering input ripple current and allowing the designer to reduce the cost of input capacitance. the example in figure 2 illustrates input currents from a two-phase converter combining to reduce the total input ripple current. figure 1. pwm and inductor-current waveforms for 2-phase converter pwm2 pwm1 i l2 i l1 i l1 + i l2 i pp v in v out ? () v out ? lf sw v in ?? --------------------------------------------------------- - = (eq. 1) i cpp , v in nv out ? ? () v out ? lf sw v ? in ? ------------------------------------------------------------------- - = (eq. 2) isl8102
10 fn9247.0 october 19, 2005 figures 25 and 26 in the section entitled input capacitor selection can be used to determine the input-capacitor rms current based on load current, duty cycle, and th e number of channels. they are provided as aids in determining the optimal input capacitor solution. pwm operation the timing of each converter leg is set by the number of active channels. the default channel setting for the isl8102 is two. one switching cycle is defined as the time between the internal pwm1 pulse termination signals. the pulse termination signal is the internally generated clock signal that triggers the fa lling edge of pwm1. the cycle time of the pulse termination signal is the inverse of the switching frequency set by the resistor between the fs pin and ground. each cycle begins when the clock signal commands pwm1 to go low. the pwm1 transition signals the internal channel 1 mosfet driver to turn off the channel 1 upper mosfet and turn on the channel 1 synchronous mosfet. in the default channel configuration, the pwm2 pulse terminates 1/2 of a cycl e after the pwm1 pulse. one switching cycle for the is l8102 is defined as the time between consecutive pwm pulse terminations (turn-off of the upper mosfet on a channel). each cycle begins when a switching clock signal commands the upper mosfet to go off. the other channel?s upper mosfet conduction is terminated 1/2 of a cycle later. once a pwm pulse transitions low, it is held low for a minimum of 1/3 cycle. this forc ed off time is required to ensure an accurate current sample. current sensing is described in the next section. after the forced off time expires, the pwm output is enabled. the pwm output state is driven by the position of t he error amplifier output signal, v comp , minus the current correction signal relative to the sawtooth ramp as illustrated in figure 3. when the modified v comp voltage crosses the sawtooth ramp, the pwm output transitions high. the internal mosfet driver detects the change in state of the pwm signal and turns off the synchronous mosfet and turns on the upper mosfet. the pwm signal will remain high until the pulse termination signal marks the begi nning of the next cycl e by triggering the pwm signal low. single phase operation can be selected by connecting 2ph to gnd. channel current balance one important benefit of multi-phase operation is the thermal advantage gained by distributing the dissipated heat over multiple devices and greater area. by doing this the designer avoids the complexity of driving parallel mosfets and the expense of using expensive he at sinks and exotic magnetic materials. in order to realize the thermal advantage, it is important that each channel in a multi-phase converter be controlled to carry about the same amount of cu rrent at any load level. to achieve this, the currents through each channel must be sampled every switching cycle. the sampled currents, i n , from each active channel are summed together and divided by the number of active ch annels. the resulting cycle average current, i avg , provides a measure of the total load- current demand on the conver ter during each switching cycle. channel current balance is achieved by comparing the sampled current of each channel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. intersil?s patented current balance method is illustra ted in figure 3, with error correction for channel 1 represen ted. in the figure, the cycle average current, i avg , is compared with the channel 1 sample, i 1 , to create an error signal i er . the filtered error signal modifies the pulse width commanded by v comp to correct any unbalance and force i er toward zero. the same method for error signal correction is applied to each active channel. current sampling in order to realize proper current balance, the currents in each channel must be sampled every switching cycle. this sampling occurs during the forced off-time, following a pwm figure 2. channel input currents and input- capacitor rms current for 2-phase converter q1 d-s current q2 d-s current c in current figure 3. channel 1 pwm function and current- balance adjustment n i avg i 2 - + + - + - f(s) pwm1 i 1 v comp sawtooth signal i er note: channel 2 is optional. filter to gate control logic isl8102
11 fn9247.0 october 19, 2005 transition low. during this time the current sense amplifier uses the isen inputs to reproduce a signal proportional to the inductor current, i l . this sensed current, i sen , is simply a scaled version of the inductor current. the sample window opens exactly 1/6 of the switching period, t sw , after the pwm transitions low. the sample window then stays open the rest of the switching cycl e until pwm transitions high again, as illustrated in figure 4. the sampled current, at the end of the t sample , is proportional to the inductor current and is held until the next switching period sample. the sampled current is used only for channel current balance. the isl8102 supports mosfet r ds(on) current sensing to sample each channel?s current for channel current balance. the internal circuitry, shown in figure 5 represents channel n of an n-channel converter. this circuitry is repeated for each channel in the converter, but may not be active depending on the status of the 2ph pin, as described in the pwm operation section. the isl8102 senses the channel load current by sampling the voltage across the lower mosfet r ds(on) , as shown in figure 5. a ground-referenced operational amplifier, internal to the isl8102, is connected to the phase node through a resistor, r isen . the voltage across r isen is equivalent to the voltage drop across the r ds(on) of the lower mosfet while it is conducting. the resu lting current into the isen pin is proportional to the channel current, i l . the isen current is sampled and held as described in the current sampling section. from figure 5, the following equation for i n is derived where i l is the channel current. output voltage setting the isl8102 uses a digital to analog converter (dac) to generate a reference voltage based on the logic signals at the ref0 and ref1 pins. the dac decodes the 2-bit logic signals into one of the discrete voltages shown in table 1. each ref0 and ref1 pins are pulled up to an internal 1.2v voltage by weak current sources (40 a current, decreasing to 0 as the voltage at the ref0, ref1 pins varies from 0 to the internal 1.2v pull-up voltage). external pull-up resistors or active-high output stages c an augment the pull-up current sources, up to a voltage of 5v. the dac pin must be connected to ref pin through a 1-5k ? resistor and a filter capacitor (0.022 f) is connected between ref and gnd. the isl8102 accommodates the use of external voltage reference connected to ref pin if a different output voltage is required. the dac voltage must be set at least as high as external reference. the error amp internal noninverting input is the lower of ref or (dac +300mv). a third method for setting the output voltage is to use a resistor divider (r p1 , r s1 ) from the output terminal (v out ) to vsen pin to set the output voltage level as shown in figure 6. this method is good for generating voltages up to 2.3v (with the ref voltage set to 1.5v). for this case, the output voltage can be obtained as follows: it is recommended to choose resistor values of less than 500 ? for r s1 and r p1 resistors in order to get better output voltage dc accuracy. figure 4. sample and hold timing time pwm i l i sen switching period sampling period old sample current new sample current figure 5. isl8102 internal and external current- sensing circuitry for current balance i n i sen i l x r ds on () r isen ------------------------- - = - + isen(n) r isen sample & hold isl8102 internal circuit external circuit v in channel n upper mosfet channel n lower mosfet - + i l x r ds on () i l table 1. isl8102 dac voltage selection table ref1 ref0 dac 0 0 0.600v 0 1 0.900v 1 0 1.200v 1 1 1.500v i n i l r ds on () r isen ---------------------- ? =(eq. 3) v out v ref r s1 r p1 + () r p1 --------------------------------- - v ofs v droop ? + ? ? = (eq. 4) isl8102
12 fn9247.0 october 19, 2005 voltage regulation in order to regulate the output voltage to a specified level, the isl8102 uses the integrating compensation network shown in figure 6. this compensation network insures that the steady state error in the output voltage is limited only to the error in the reference voltage (output of the dac or the external voltage reference) and offset errors in the ofs current source, remote sense and error amplifiers. intersil specifies the guaranteed tolerance of the isl8102 to include the combined tolerances of each of these elements, except when an external reference or volt age divider is used, then the tolerances of these components has to be taken into account. the isl8102 incorporates an internal differential remote sense amplifier in the feedback path. the amplifier removes the voltage error encountered when measuring the output voltage relative to the controller ground reference point, resulting in a more accurate means of sensing output voltage. connect the load?s output sense pins to the non-inverting input, vsen, and inverting input, rgnd, of the remote sense amplifier. the droop voltage, v droop , also feeds into the remote sense amplifier. the remote sense output, v diff , is therefore equal to the sum of the output voltage, v out , and the droop voltage. v diff is connected to the inverting input of the error amplifier through an external resistor. the output of the error amplifier, v comp , is compared to the sawtooth waveform to generate the pwm signals. the pwm signals control the timing of the internal mosfet drivers and regulate the converter output so that the voltage at fb is equal to the voltage at ref. this will regulate the output voltage to be equal to equation 5. the internal and external circuitry that controls voltage regulation is illustrated in figure 6. load-line (droop) regulation in some high current applications, a requirement on a precisely controlled output impedance is imposed. this dependence of output voltage on load current is often termed ?droop? or ?load line? regulation. the droop is an optional feature in the isl8102. it can be enabled by connecting icomp pin to droop pin as shown in figure 6. to disable it, connect the droop pin to iref pin. as shown in figure 6, a voltage, v droop , proportional to the total current in all active channels, i out , feeds into the differential remote-sense amplifier. the resulting voltage at the output of the remote-sense amplifier is the sum of the output voltage and the droop voltage. as equation 5 shows, feeding this voltage into the compensation network causes the regulator to adjust the output voltage so that it?s equal to the reference voltage minus the droop voltage. the droop voltage, v droop , is created by sensing the current through the output inductors. this is accomplished by using a continuous dcr current sensing method. inductor windings have a ch aracteristic distributed resistance or dcr (direct current resistance). for simplicity, the inductor dcr is considered as a separate lumped quantity, as shown in figure 7. the channel current, i l , flowing through the inductor, passes through the dcr. equation 6 shows the s-domain equivalent voltage, v l , across the inductor. the inductor dcr is important because the voltage dropped across it is proportional to the channel current. by using a simple r-c network and a current sense amplifier, as shown in figure 7, the voltage drop across all of the inductors dcrs can be extracted. the output of the current sense amplifier, v droop , can be shown to be proportional to the channel currents i l1 and i l2 , shown in equation 7. figure 6. output voltage and load-line regulation with offset adjustment i ofs external circuit isl8102 internal circuit comp r 2 r 1 fb vdiff vsen rgnd - + v ofs error amplifier - + differential remote-sense amplifier v comp c 1 ref c ref - + vid dac iref droop + - + v droop - + v out - dac icomp + - isum isense amp r p1 r s1 c sum v out v ref v ofs v droop ? = (eq. 5) v l s () i l sl dcr + ? () ? = (eq. 6) v droop s () sl ? dcr ------------- 1 + ?? ?? sr comp c comp ?? 1 + () -------------------------------------------------------------------------- r comp r s ----------------------- i l1 i l2 + () dcr ?? ? = (eq. 7) isl8102
13 fn9247.0 october 19, 2005 if the r-c network components are selected such that the r-c time constant matches the inductor l/dcr time constant, then v droop is equal to the sum of the voltage drops across the individual dcrs, multiplied by a gain. as equation 8 shows, v droop is therefore proportional to the total output current, i out . by simply adjusting the value of r s , the load line can be set to any level, giving the converter the right amount of droop at all load currents. it may also be necessary to compensate for any changes in dcr due to temperature. these changes cause the load line to be ske wed, and cause the r-c time constant to not match the l/dcr time constant. if this becomes a problem a simple negative temperature coefficient resistor network can be used in the place of r comp to compensate for the rise in dcr due to temperature. output voltage offset programming the isl8102 allows the designer to accurately adjust the offset voltage by connecting a resistor, r ofs , from the ofs pin to vcc or gnd. when r ofs is connected between ofs and vcc, the voltage across it is regulated to 1.5v. this causes a proportional current (i ofs ) to flow into the ofs pin and out of the fb pin. if r ofs is connected to ground, the voltage across it is regulated to 0.5v, and i ofs flows into the fb pin and out of the ofs pin. the offset current flowing through the resistor between vdiff and fb will generate the desired offset voltage which is equal to the product (i ofs x r 1 ). these functions are shown in figures 8 and 9. once the desired output offset voltage has been determined, use the following formulas to set r ofs : for positive offset (connect r ofs to gnd): for negative offset (connect r ofs to vcc): v droop r comp r s --------------------- i out dcr ?? = (eq. 8) figure 7. dcr sensing configuration - + icomp dcr l inductor v out c out i l 1 - + v l (s) dcr l inductor phase1 phase2 i l 2 r s r s r comp c comp isum iref isl8102 - + v droop i out droop c sum (optional) (eq. 9) r ofs 0.5 r 1 ? v offset -------------------------- = (eq. 10) r ofs 1.5 r 1 ? v offset -------------------------- = e/a fb ofs vcc gnd + - + - 0.5v 1.5v gnd r ofs r 1 vdiff isl8102 figure 8. positive offset output voltage programming vref v ofs + - i ofs e/a fb ofs vcc gnd + - + - 0.5v 1.5v vcc r ofs r 1 vdiff isl8102 vref v ofs + - i ofs figure 9. negative offset output voltage programming isl8102
14 fn9247.0 october 19, 2005 advanced adaptive zero shoot-through deadtime control (patent pending) the integrated drivers incorporate a unique adaptive deadtime control technique to minimize deadtime, resulting in high efficiency from the reduced freewheeling time of the lower mosfet body-diode conduction, and to prevent the upper and lower mosfets from conducting simultaneously. this is accomplished by ensuring either rising gate turns on its mosfet with minimum and sufficient delay after the other has turned off. during turn-off of the lowe r mosfet, the phase voltage is monitored until it reaches a -0.3v/+0.8v trip point for a forward/reverse current, at which time the ugate is released to rise. an auto-zero comparator is used to correct the r ds(on) drop in the phase voltage pr eventing false detection of the -0.3v phase level during r ds(on) conduction period. in the case of zero current, the ugate is released after 35ns delay of the lgate dropping below 0.5v. during the phase detection, the disturbance of lgate falli ng transition on the phase node is blanked out to prevent fals ely tripping. once the phase is high, the advanced adaptive shoot-through circuitry monitors the phase and ugate voltages during a pwm falling edge and the subsequent ugate turn-off. if either the ugate falls to less than 1.75v ab ove the phase or the phase falls to less than +0.8v, the lgate is released to turn on. internal bootstrap device the two integrated drivers feat ure an internal bootstrap schottky diode. simply adding an external capacitor across the boot and phase pins comple tes the bootstrap circuit. the bootstrap function is also designed to prevent the bootstrap capacitor from overcharging due to the large negative swing at the phase node. this reduces voltage stress on the boot to phase pins. the bootstrap capacitor must have a maximum voltage rating above pvcc + 5v and its capacitance value can be chosen from the following equation: where q g1 is the amount of gate charge per upper mosfet at v gs1 gate-source voltage and n q1 is the number of control mosfets. the ? v boot_cap term is defined as the allowable droop in the rail of the upper gate drive. figure 10 shows the boot capacitor ripple voltage as a function of boot capacitor value and total upper mosfet gate charge. gate drive voltage versatility the isl8102 provides the user flexibility in choosing the gate drive voltage for efficiency optimization. the controller ties the upper and lower drive rails together. simply applying a voltage from 5v up to 12v on pvcc sets both gate drive rail voltages simultaneously. initialization prior to initialization, proper conditions must exist on the enll, vcc, pvcc and the ref0 and ref1 pins. when the conditions are met, the controller begins soft-start. once the output voltage is within the proper window of operation, the controller asserts pgood. enable and disable while in shutdown mode, the pwm outputs are held in a high-impedance state to assure the drivers remain off. the following input conditions must be met before the isl8102 is released from shutdown mode. 1. the bias voltage applied at vcc must reach the internal power-on reset (por) rising threshold. once this threshold is reached, proper operation of all aspects of the isl8102 is guaranteed. h ysteresis between the rising and falling thresholds assure that once enabled, the isl8102 will not inadvertently turn off unless the bias voltage drops substantially (see electrical specifications ). c boot_cap q gate ? v boot_cap -------------------------------------- q gate q g1 pvcc ? v gs1 ---------------------------------- n q1 ? = (eq. 11) 50nc 20nc figure 10. bootstrap capacitance vs boot ripple voltage ? v boot_cap (v) c boot_cap ( f) 1.6 1.4 1.2 1. 0.8 0.6 0.4 0.2 0.0 0.3 0.0 0.1 0.2 0.4 0.5 0.6 0.9 0.7 0.8 1.0 q gate = 100nc isl8102
15 fn9247.0 october 19, 2005 2. the voltage on enll must be above 0.66v. the en input allows for power sequencing between the controller bias voltage and another voltage rail. the enable comparator holds the isl8102 in shutdown until the voltage at enll rises above 0.66v. the enable comparator has 100mv of hysteresis to prevent bounce. 3. the driver bias voltage applied at the pvcc pins must reach the internal power-on reset (por) rising threshold. in order for the isl8102 to begin operation, pvcc is the only pin that is required to have a voltage applied that exceeds por. hysteresis bet ween the rising and falling thresholds assure that once enabled, the isl8102 will not inadvertently turn off unless the pvcc bias voltage drops substantially (see electrical specifications ). when each of these conditions is true, the controller immediately begins the soft-start sequence. soft-start during soft-start, the dac volt age ramps linearly from zero to the programmed level. the pwm signals remain in the high-impedance state until the controller detects that the ramping dac level has reached the output-voltage level. this protects the system against the large, negative inductor currents that would otherwise occur when starting with a pre- existing charge on the output as the controller attempted to regulate to zero volts at the be ginning of the soft-start cycle. the output soft-start time, t ss , begins with a delay period equal to 64 switching cycles after the enll has exceeded its por level, followed by a linear ramp with a rate determined by the switching period, 1/f sw . for example, a regulator with 450khz switching frequency having ref voltage set to 1.2v has t ss equal to 3.55ms. a 100mv offset exists on the remote-sense amplifier at the beginning of soft-start and ramps to zero during the first 640 cycles of soft-start (704 cycl es following enable). this prevents the large inrush curre nt that would otherwise occur should the output voltage star t out with a slight negative bias. during the first 640 cycles of soft-start (704 cycles following enable) the dac voltage increments the reference in 25mv steps. the remainder of soft-start sees the dac ramping with 12.5mv steps. the isl8102 also has the ability to start up into a pre- charged output as shown in fi gure 12, without causing any unnecessary disturbance. the fb pin is monitored during soft-start, and should it be higher than the equivalent internal ramping reference voltage, the output drives hold both mosfets off. once the internal ramping reference exceeds the fb pin potential, the outpu t drives are enabled, allowing the output to ramp from the pr e-charged level to the final level dictated by the reference setting. should the output be pre-charged to a level exceeding the reference setting, the output drives are enabled at the end of the soft-start period, leading to an abrupt correction in the output voltage down to the ?reference set? level. fault monitoring and protection the isl8102 actively monitors output voltage and current to detect fault conditions. fault monitors trigger protective measures to prevent damage to the sensitive load. one common power good indicator is provided for linking to external system monitors. the schematic in figure 13 outlines the interaction between the fault monitors and the power good signal. figure 11. power sequencing using threshold- sensitive enable (enll) function - + 0.66v external circuit isl8102 internal circuit enll +12v por circuit 10.7k ? 1.40k ? enable comparator soft-start and fault logic vcc pvcc t ss 64 dac + 1280 ? f sw -------------------------------------------- = (eq. 12) figure 12. soft-start waveforms for isl8102-based multi-phase converter enll (5v/div) v out (0.5v/div) gnd> t1 gnd> t2 t3 output precharged below dac level output precharged above dac level isl8102
16 fn9247.0 october 19, 2005 power good signal the power good pin (pgood) is an open-drain logic output that transitions high when t he converter is operating after soft-start. pgood pulls low during shutdown and releases high after a successful soft-s tart. pgood transitions low when an undervoltage, overvoltage, or overcurrent condition is detected or when the controller is disabled by a reset from enll or por. if after an under voltage or overvoltage event occurs the output returns to within under and overvoltage limits, pgood will return high. undervoltage detection the undervoltage threshold is set at 82% of the ref voltage. when the out put voltage (vsen-rgnd) is below the undervoltage threshold, pgood gets pulled low. no other action is taken by the controller. pgood will return high if the output voltage rises above 85% of the ref voltage. overvoltage protection the isl8102 constantly monito rs the difference between the vsen and rgnd voltages to detect if an overvoltage event occurs. during soft-start, while the dac/ref is ramping up, the overvoltage trip level is t he higher of ref plus 150mv or a fixed voltage, v ovp . the fixed voltage, v ovp , is 1.67v. upon successful soft-start, the over voltage trip level is only ref plus 150mv. ovp releases 50mv below its trip point if it was ?ref plus 150mv? that tripped it, and releases 100mv below its trip point if it was the fixed voltage, v ovp , that tripped it. actions are taken by the isl8102 to protect the load when an overvoltage condition occurs, unt il the output voltage falls back within set limits. at the inception of an overvolt age event, all lgate signals are commanded high, and the pgood signal is driven low. this causes the controller to turn on the lower mosfets and pull the output voltage below a level that might cause damage to the load. the lgate outputs remain high until vdiff falls to within the overvoltage limits explained above. the isl8102 will continue to protect the load in this fashion as long as the overvoltage condition recurs. once an overvoltage condition ends the isl8102 continues normal operation and pgood returns high. pre-por overvoltage protection prior to pvcc and vcc exceeding their por levels, the isl8102 is designed to protect the load from any overvoltage events that may occur. this is accomplished by means of an internal 10k ? resistor tied from phase to lgate, which turns on the lower mosfet to control the output voltage until the overvoltage event ceases or the input power supply cuts off. for complete protection, the low side mosfet should have a gate threshold well below the maximum voltage rating of the load/microprocessor. in the event that during normal operation the pvcc or vcc voltage falls back below the por threshold, the pre-por overvoltage protection circuitry reactivates to protect from any more pre-por overvoltage events open sense line protection in the case that either of the remote sense lines, vsen or gnd, become open, the isl8102 is designed to detect this and shut down the controller. this event is detected by monitoring the voltage on the iref pin, which is a local version of v out sensed at the output s of the inductors. if vsen or rgnd become opened, vdiff falls, causing the duty cycle to increase and the output voltage on iref to increase. if the voltage on iref exceeds ?vdiff+1v?, the controller will shut down. once the voltage on iref falls below ?vdiff+1v?, the isl8102 will restart at the beginning of soft-start. overcurrent protection the isl8102 detects overcurrent events by comparing the droop voltage, v droop , to the ocset voltage, v ocset , as shown in figure 13. the droop voltage, set by the external current sensing circuitry, is pr oportional to the output current as shown in equation 8. a constant 100 a flows through r ocset , creating the ocset voltage. when the droop voltage exceeds the ocset voltage, the overcurrent protection circuitry activates. since the droop voltage is figure 13. power good and protection circuitry - + dac + 150mv vsen - + 0.82 x dac ov uv pgood soft-start, fault and control logic - + oc - + isen iref isum icomp ocset r ocset + - v droop v ocset + - v ovp 100a isl8102 internal circuitry - + rgnd x1 - + +1v vdiff droop* *connect droop to iref to disable the droop feature isl8102
17 fn9247.0 october 19, 2005 proportional to the output curren t, the overcurrent trip level, i max , can be set by selecting the proper value for r ocset , as shown in equation 13. once the output current exceeds the overcurrent trip level, v droop will exceed v ocset , and a comparator will trigger the converter to begin overcurre nt protection procedures. at the beginning of overcurrent sh utdown, the controller turns off both upper and lower mosfets. the system remains in this state for a period of 4096 switching cycles. if the controller is still enabled at the en d of this wait period, it will attempt a soft-start (as shown in figure 14). if the fault remains, the trip-retry cycles will continue indefinitely until either the controller is disabled or the fault is cleared. note that the energy delivered during trip-retry cycling is much less than during full-load operation, so there is no thermal hazard. general design guide this design guide is intended to provide a high-level explanation of the steps necessa ry to create a multi-phase power converter. it is assumed that the reader is familiar with many of the basic skills and techniques referenced below. in addition to this guide, intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for many applications. power stages the first step in designing a multi-phase converter is to determine the number of phases. this determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board, whether through-hole components are permitted, the total board space available for power-supply circuitry, and the maximum amount of load current. generally speaking, the most economical soluti ons are those in which each phase handles between 25 and 30a. all surface-mount designs will tend toward the lower end of this current range. if through-hole mosfets and inductors can be used, higher per-phase currents are possible. in cases where board space is the limiting constraint, current can be pushed as high as 40a per phase, but thes e designs require heat sinks and forced air to cool the mosfets, inductors and heat- dissipating surfaces. mosfets the choice of mosfets depends on the current each mosfet will be required to con duct, the switching frequency, the capability of the mosfets to dissipate heat, and the availability and nature of heat sinking and air flow. lower mosfet power calculation the calculation for the approximate power loss in the lower mosfet can be simplified, since virtually all of the loss in the lower mosfet is due to current conducted through the channel resistance (r ds(on) ). in equation 14, i m is the maximum continuous output current, i pp is the peak-to-peak inductor current (see equation 1), and d is the duty cycle (v out /v in ). an additional term can be added to the lower-mosfet loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-mosfet body diode. this term is dependent on the diode forward voltage at i m , v d(on) , the switching frequency, f sw , and the length of dead times, t d1 and t d2 , at the beginning and the end of the lower-mosfet conduction interval respectively. the total maximum power dissipated in each lower mosfet is approximated by the summation of p low,1 and p low,2 . upper mosfet power calculation in addition to r ds(on) losses, a large portion of the upper- mosfet losses are due to currents conducted across the input voltage (v in ) during switching. since a substantially higher portion of the upper-mosfet losses are dependent on switching frequency, the power calculation is more complex. upper mosfet losses can be divided into separate components involving the upper-mosfet switching times, the lower-mosfet body-diode reverse- recovery charge, q rr , and the upper mosfet r ds(on) conduction loss. r ocset i max r comp dcr ?? 100 ar s ? ---------------------------------------------------------- = (eq. 13) 0a 0v output current figure 14. overcurrent behavior in hiccup mode output voltage p low 1 , r ds on () i m n ----- - ?? ?? ?? 2 1d ? () ? i lpp , 2 1d ? () ? 12 ------------------------------------ - + ? = (eq. 14) p low 2 , v don () f sw i m n ----- - i pp 2 -------- - + ?? ?? t d1 ? i m n ----- - i pp 2 -------- - ? ?? ?? t d2 ? + ?? = (eq. 15) isl8102
18 fn9247.0 october 19, 2005 when the upper mosfet turns off, the lower mosfet does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. once the lower mosfet begins conducting, the current in the upper mosfet falls to zero as the current in the lower mosfet ramps up to assume the full inductor current. in equation 16, the required time for this commutation is t 1 and the approximated associated power loss is p up,1 . at turn on, the upper mosfet begins to conduct and this transition occurs over a time t 2 . in equation 17, the approximate power loss is p up,2 . a third component involves the lower mosfet reverse- recovery charge, q rr . since the inductor current has fully commutated to the upper mosfet before the lower- mosfet body diode can recover all of q rr , it is conducted through the upper mosfet across vin. the power dissipated as a result is p up,3 . finally, the resistive part of the upper mosfet is given in equation 19 as p up,4 . the total power dissipated by the upper mosfet at full load can now be approximated as the summation of the results from equations 16, 17, 18 and 19. since the power equations depend on mosfet parameters, choosing the correct mosfets can be an it erative process involving repetitive solutions to the loss equations for different mosfets and different switching frequencies. package power dissipation when choosing mosfets it is important to consider the amount of power being dissipat ed in the integrated drivers located in the controller. since there are a total of two drivers in the controller package, the total power dissipated by both drivers must be less than the maximum allowable power dissipation for the qfn package. calculating the power dissipatio n in the drivers for a desired application is critical to ensure safe operation. exceeding the maximum allowable power dissipation level will push the ic beyond the maximum recommended operating junction temperature of 125 c. the maximum allowable ic power dissipation for the 5x5 qfn package is approximately 4w at room temperature. see layout considerations paragraph for thermal transfer improvement suggestions. when designing the isl8102 into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected mosfets. the total gate drive power losses, p qg_tot , due to the gate charge of mosfets and the integrated driver?s internal circuitry and their corresponding average driver current can be estimated with equations 20 and 21, respectively. in equations 20 and 21, p qg_q1 is the total upper gate drive power loss and p qg_q2 is the total lower gate drive power loss; the gate charge (q g1 and q g2 ) is defined at the particular gate to source drive voltage pvcc in the corresponding mosfet data sheet; i q is the driver total quiescent current with no load at both drive outputs; n q1 and n q2 are the number of upper and lower mosfets per phase, respectively; n phase is the number of active phases. the i q* vcc product is the quiescent power of the controller without capacitive load and is typically 75mw at 300khz. the total gate drive power losses are dissipated among the resistive components along the transition path and in the bootstrap diode. the portion of the total power dissipated in the controller itself is the power dissipated in the upper drive path resistance, p dr_up , the lower drive path resistance, p dr_low , and in the boot strap diode, p boot . the rest of the power will be dissipated by the external gate resistors (r g1 and r g2 ) and the internal gate resistors (r gi1 and r gi2 ) of the mosfets. figures 15 and 16 show the typical upper and lower gate drives turn-on transition path. the total power dissipation in the controller itself, p dr , can be roughly estimated as: p up 1 , v in i m n ----- - i pp 2 -------- - + ?? ?? t 1 2 ---- ?? ?? ?? f sw ??? (eq. 16) p up 2 , v in i m n ----- - i pp 2 -------- - ? ?? ?? t 2 2 ---- ?? ?? ?? f sw ??? (eq. 17) p up 3 , v in q rr f sw ?? = (eq. 18) p up 4 , r ds on () i m n ----- - ?? ?? ?? 2 d ? i pp 2 12 --------- - + ? (eq. 19) p qg_tot p qg_q1 p qg_q2 i q vcc ? ++ = (eq. 20) p qg_q1 3 2 -- - q g1 pvcc f sw n q1 n phase ?? ??? = p qg_q2 q g2 pvcc f sw n q2 n phase ???? = i dr 3 2 -- - q g1 n ? q1 ? q g2 n q2 ? + ?? ?? n phase f sw i q + ?? = (eq. 21) p dr p dr_up p dr_low p boot i q vcc ? () +++ = (eq. 22) p dr_up r hi1 r hi1 r ext1 + -------------------------------------- r lo1 r lo1 r ext1 + ---------------------------------------- + ?? ?? ?? p qg_q1 3 --------------------- ? = p dr_low r hi2 r hi2 r ext2 + -------------------------------------- r lo2 r lo2 r ext2 + ---------------------------------------- + ?? ?? ?? p qg_q2 2 --------------------- ? = r ext1 r g1 r gi1 n q1 ------------- + = r ext2 r g2 r gi2 n q2 ------------- + = p boot p qg_q1 3 --------------------- = isl8102
19 fn9247.0 october 19, 2005 current balancing component selection the isl8102 senses the channel load current by sampling the voltage across the lower mosfet r ds(on) , as shown in figure 17. the isen pins are denoted isen1, and isen2. the resistors connected between these pins and the respective phase nodes determine the gains in the channel current balance loop. select values for these resistors based on the room temperature r ds(on) of the lower mosfets; the full-load operating current, i fl ; and the number of phases, n using equation 23. in certain circumstances, it ma y be necessary to adjust the value of one or more isen re sistors. when the components of one or more channels are inhibited from effectively dissipating their heat so that the affected channels run hotter than desired, choose new, smaller values of r isen for the affected phases (see the section entitled channel current balance ). choose r isen,2 in proportion to the desired decrease in temperature rise in order to c ause proportionally less current to flow in the hotter phase. in equation 24, make sure that ? t 2 is the desired temperature rise above the ambient temperature, and ? t 1 is the measured temperature rise above the am bient temperature. while a single adjustment according to equation 24 is usually sufficient, it may occasionally be necessary to adjust r isen two or more times to achieve optimal thermal balance between all channels. load line regulation component selection (dcr current sensing) for accurate load line regulation, the isl8102 senses the total output current by detect ing the voltage across the output inductor dcr of each channel (as described in the load line regulation section). as figure 18 illustrates, an r-c network is required to ac curately sense the inductor dcr voltage and convert this information into a ?droop? voltage, which is proportional to the total output current. choosing the components for this current sense network is a two step process. first, r comp and c comp must be chosen so that the time constant of this r comp -c comp network matches the time cons tant of the inductor l/dcr. then the resistor r s must be chosen to set the current sense network gain, obtaining the desired full load droop voltage. follow the steps below to choose the component values for this r-c network. 1. choose an arbitrary value for c comp . the recommended value is 0.01 f. 2. plug the inductor l and dcr component values, and the values for c comp chosen in steps 1, into equation 25 to calculate the value for r comp . 3. use the new value for r comp obtained from equation 25, as well as the desired full load current, i fl , full load droop voltage, v droop , and inductor dcr in equation 26 to calculate the value for r s . figure 15. typical upper-gate drive turn-on path figure 16. typical lower-gate drive turn-on path q1 d s g r gi1 r g1 boot r hi1 c ds c gs c gd r lo1 phase pvcc ugate pvcc q2 d s g r gi2 r g2 r hi2 c ds c gs c gd r lo2 lgate figure 17. isl8102 internal and external current- sensing circuitry isen(n) r isen v in channel n upper mosfet channel n lower mosfet - + i l x r ds on () i l isl8102 r isen r ds on () 50 10 6 ? ? ----------------------- i fl n ------- - ? = (eq. 23) r isen 2 , r isen ? t 2 ? t 1 ---------- ? = (eq. 24) r comp l dcr c comp ? --------------------------------------- = (eq. 25) r s i fl v droop ------------------------ - r comp dcr ?? = (eq. 26) isl8102
20 fn9247.0 october 19, 2005 due to errors in the inductance or dcr it may be necessary to adjust the value of r comp to match the time constants correctly. the effects of time co nstant mismatch can be seen in the form of droop overs hoot or undershoot during the initial load transient spike, as shown in figure 19. follow the steps below to ensure the r-c and inductor l/dcr time constants are matched accurately. 1. capture a transient event with the oscilloscope set to about l/dcr/2 (sec/div). for example, with l = 1 h and dcr = 1m ? , set the oscilloscope to 500 s/div. 2. record ? v 1 and ? v 2 as shown in figure 19. 3. select a new value, r comp,2 , for the time constant resistor based on the original value, r comp,1 , using the following equation. 4. replace r comp with the new value and check to see that the error is corrected. repeat the procedure if necessary. after choosing a new value for r comp , it will most likely be necessary to adjust the value of r s to obtain the desired full load droop voltage. use equation 26 to obtain the new value for r s . compensation the two opposing goals of compensating the voltage regulator are stability and speed. depending on whether the regulator employs the optional load-line regulation as described in load-line regulation, there are two distinct methods for achieving these goals. compensating the load-line regulated converter the load-line regulated converter behaves in a similar manner to a peak current m ode controller because the two poles at the output filt er l-c resonant frequency split with the introduction of current informat ion into the control loop. the final location of th ese poles is determ ined by the system function, the gain of the current signal, and the value of the compensation components, r 2 and c 1 . since the system poles and zero are affected by the values of the components that are me ant to compensate them, the solution to the system equation becomes fairly complicated. fortunately, there is a simple approximation that comes very close to an optimal solution. treating the system as though it were a voltage-mode regulator, by compensating the l-c poles and the esr zero of the voltage mode approximation, figure 18. dcr sensing configuration - + icomp dcr l inductor v out c out i l 1 - + v l (s) dcr l inductor phase1 phase2 i l 2 r s r s r comp c comp isum iref isl8102 - + v droop i out droop r comp 2 , r comp 1 , v 1 ? v 2 ? ---------- ? = (eq. 27) figure 19. time constant mismatch behavior ? v 1 v out i tran ? v 2 ? i figure 20. compensation configuration for load-line regulated isl8102 circuit isl8102 comp c 1 r 2 r 1 fb vdiff c 2 (optional) isl8102
21 fn9247.0 october 19, 2005 yields a solution that is always stable with very close to ideal transient performance. the feedback resistor, r 1 , has already been chosen as outlined in load-line regulation resistor. select a target bandwidth for the co mpensated system, f 0 . the target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the per- channel switching frequency. the values of the compensation components depend on the relationships of f 0 to the l-c pole frequency and the esr zero frequency. for each of the following three, there is a separate set of equations for the compensation components. in equations 28, l is the per-channel filter inductance divided by the number of active channels; c is the sum total of all output capacitors; esr is the equivalent series resistance of the bulk output filter capacitance; and v osc is the peak-to-peak sawtooth signal amplitude as described in the electrical specifications . once selected, the compensation values in equations 28 assure a stable converter with reasonable transient performance. in most cases, transient performance can be improved by making adjustments to r 2 . slowly increase the value of r 2 while observing the transient performance on an oscilloscope until no further improvement is noted. normally, c 1 will not need adjustment. keep the value of c 1 from equations 28 unless some performance issue is noted. the optional capacitor c 2 , is sometimes needed to bypass noise away from the pwm comparator (see figure 20). keep a position available for c 2 , and be prepared to install a high frequency capacitor of between 22pf and 150pf in case any leading edge jitter problem is noted. compensating the converter operating without load-line regulation the isl8102 multi-phase conver ter operating without load line regulation behaves in a similar manner to a voltage- mode controller. this section highlights the design consideration for a voltage-mode controller requiring external compensation. to address a broad range of applications, a type-3 feedback network is recommended (see figure 21). figure 22 highlights the voltage-mode control loop for a synchronous-rectified buck converter, applicable, with a small number of adjustments, to the multi-phase isl8102 circuit. the output voltage (v out ) is regulated to the reference voltage, vref, level. the error amplifier output (comp pin voltage) is compar ed with the oscillator (osc) modified saw-tooth wave to provide a pulse-width modulated wave with an amplitude of v in at the phase node. the pwm wave is smoothed by the output filter (l and c). the output filter capacitor bank?s equivalent series resistance is represented by the series resistor esr. the modulator transfer function is the small-signal transfer function of v out /v comp . this function is dominated by a dc gain, given by d max v in /v osc , and shaped by the output filter, with a double pole break frequency at f lc and a zero at f ce . for the purpose of this analysis, l and dcr represent the individual channel inductance and its dcr divided by 2 (equivalent parallel value of the two output inductors), while c and esr represents the total output capacitance and its equivalent series resistance. 1 2 lc ? ? --------------------------- f 0 > r 2 r 1 2 f 0 v osc lc ? ?? ? 0.66 v in ? ----------------------------------------------------------- - ? = c 1 0.66 v in ? 2 v osc r 1 f 0 ??? ------------------------------------------------ - = case 1: 1 2 lc ? ? --------------------------- f 0 1 2 cesr ?? --------------------------------- < r 2 r 1 v osc 2 () 2 f 0 2 lc ???? 0.66 v in ? --------------------------------------------------------------- - ? = c 1 0.66 v in ? 2 () 2 f 0 2 v osc r 1 lc ? ?? ? ? ------------------------------------------------------------------------------- - = case 2: (eq. 28) f 0 1 2 c esr ?? --------------------------------- > r 2 r 1 2 f 0 v osc l ?? ? 0.66 v in esr ?? ----------------------------------------------- ? = c 2 0.66 v in esr c ?? ? 2 v osc r 1 f 0 l ???? -------------------------------------------------------------- - = case 3: figure 21. compensation configuration for non-load-line regulated isl8102 circuit isl8102 comp c 1 r 2 r 1 fb vdiff c 2 r 3 c 3 f lc 1 2 lc ? ? --------------------------- = f ce 1 2 c esr ?? --------------------------------- = isl8102
22 fn9247.0 october 19, 2005 the compensation network consists of the error amplifier (internal to the isl8102) and the external r 1 -r 3 , c 1 -c 3 components. the goal of the compensation network is to provide a closed loop transfer function with high 0db crossing frequency (f 0 ; typically 0.1 to 0.3 of f sw ) and adequate phase margin (better than 45 degrees). phase margin is the difference between the closed loop phase at f 0db and 180. the equations that follow relate the compensation network?s poles, zeros and gain to the components (r 1 , r 2 , r 3 , c 1 , c 2 , and c 3 ) in figures 20 and 21. use the following guidelines for locating the poles and zeros of the compensation network: 1. select a value for r 1 (1k ? to 5k ? , typically). calculate value for r 2 for desired converter bandwidth (f 0 ). if setting the output voltage to be equal to the reference set voltage as shown in figure 22, the design procedure can be followed as presented. however, when setting the output voltage via a resistor di vider placed at the input of the differential amplifier (as shown in figure 6), in order to compensate for the attenu ation introduced by the resistor divider, the obtained r 2 value needs be multiplied by a factor of (r p1 +r s1 )/r p1 . the remainder of the calculations remain unchanged, as long as the compensated r 2 value is used. 2. calculate c 1 such that f z1 is placed at a fraction of the f lc , at 0.1 to 0.75 of f lc (to adjust, change the 0.5 factor to desired number). the higher t he quality factor of the output filter and/or the higher the ratio f ce /f lc , the lower the f z1 frequency (to maximize phase boost at f lc ). 3. calculate c 2 such that f p1 is placed at f ce . 4. calculate r 3 such that f z2 is placed at f lc . calculate c 3 such that f p2 is placed below f sw (typically, 0.5 to 1.0 times f sw ). f sw represents the per-channel switching frequency. change the numerical factor to re flect desired placement of this pole. placement of f p2 lower in frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the hf ripple component at the comp pin and minimizing re sultant duty cycle jitter. it is recommended that a mathematical model is used to plot the loop response. check the loop gain against the error amplifier?s open-loop gain. verify phase margin results and adjust as necessary. the following equations describe the frequency response of the modulator (g mod ), feedback compensation (g fb ) and closed-loop response (g cl ): compensation break frequency equations figure 23 shows an asymptotic plot of the dc/dc converter?s gain vs. frequency. the actual modulator gain has a high gain peak dependent on the quality fact or (q) of the output filter, which is not shown. using the above guidelines should yield a compensation gain similar to the curve plotted. the open loop error amplifier gain bounds the compensation gain. check the compensation gain at f p2 against the capabilities of the error figure 22. voltage-mode buck converter compensation design - + e/a vref comp c 1 r 2 r 1 fb c 2 r 3 c 3 l c v in pwm circuit half-bridge drive oscillator esr external circuit isl8102 v out v osc dcr ugate phase lgate - + vdiff vsen rgnd r 2 v osc r 1 f 0 ?? d max v in f lc ?? --------------------------------------------- = c 1 1 2 r 2 0.5 f lc ?? ? ---------------------------------------------- - = c 2 c 1 2 r 2 c 1 f ce 1 ? ??? -------------------------------------------------------- = r 3 r 1 f sw f lc ------------ 1 ? --------------------- - = c 3 1 2 r 3 0.7 f sw ?? ? ------------------------------------------------ - = g mod f () d max v in ? v osc ----------------------------- - 1sf () esr c ?? + 1sf () esr dcr + () c ?? s 2 f () lc ?? ++ ----------------------------------------------------------------------------------------------------------- ? = g fb f () 1sf () r 2 c 1 ?? + sf () r 1 c 1 c 2 + () ?? ---------------------------------------------------- ? = 1sf () r 1 r 3 + () c 3 ?? + 1sf () r 3 c 3 ?? + () 1sf () r 2 c 1 c 2 ? c 1 c 2 + -------------------- - ?? ?? ?? ?? + ?? ?? ?? ? ------------------------------------------------------------------------------------------------------------------------- g cl f () g mod f () g fb f () ? = where s f () , 2 fj ?? = f z1 1 2 r 2 c 1 ?? ------------------------------ - = f z2 1 2 r 1 r 3 + () c 3 ?? ------------------------------------------------- = f p1 1 2 r 2 c 1 c 2 ? c 1 c 2 + -------------------- - ?? -------------------------------------------- - = f p2 1 2 r 3 c 3 ?? ------------------------------ - = isl8102
23 fn9247.0 october 19, 2005 amplifier. the closed loop gain, g cl , is constructed on the log-log graph of figure 23 by adding the modulator gain, g mod (in db), to the feedback compensation gain, g fb (in db). this is equivalent to multiplying the modulator transfer function and the compensation transfer function and then plotting the resulting gain. a stable control loop has a gain crossing with close to a -20db/decade slope and a phase margin greater than 45 degrees. include worst case component variations when determining phase margin. the mathematical model presented makes a number of approximations and is generally not accurate at frequencies approaching or exceeding half the switching frequency. when designing compensation networks, select target crossover frequencies in the range of 10% to 30% of the per-channel switching frequency, f sw . output filter design the output inductors and the output capacitor bank together to form a low-pass filter re sponsible for smoothing the pulsating voltage at the phase nodes. the output filter also must provide the transient ene rgy until the regulator can respond. because it has a low bandwidth compared to the switching frequency, the outp ut filter limits the system transient response. the output capacitors must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. in high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. output filter design begins with minimizing the cost of this part of the circuit. the critical load parameters in choosing the output capacitors are the maximum size of the load step, ? i, the load-current slew rate, di/dt, and the maximum allowable output-voltage deviation under transient loading, ? v max . capacitors are characterized according to their capacitance, esr, and esl (equivalent series inductance). at the beginning of the load tr ansient, the output capacitors supply all of the transient current. the output voltage will initially deviate by an amount approximated by the voltage drop across the esl. as the load current increases, the voltage drop across the esr increases linearly until the load current reaches its final value. the capacitors selected must have sufficiently low esl and esr so that the total output- voltage deviation is less than the allowable maximum. neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount the filter capacitor must have sufficiently low esl and esr so that ? v < ? v max . most capacitor solutions rely on a mixture of high frequency capacitors with relatively lo w capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. minimizing the esl of the high-frequency capacitors allows them to support the output voltage as the current increases. minimizing the esr of the bulk capacitors allows them to supply the increased current with less output voltage deviation. the esr of the bulk capacitors also creates the majority of the output-voltage ripple. as th e bulk capacitors sink and source the inductor ac ripple current (see interleaving and equation 2), a voltage develops across the bulk capacitor esr equal to i c,pp (esr). thus, once the output capacitors are selected, the maximum allowable ripple voltage, v pp(max) , determines the lower limit on the inductance. since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. the output inductors must be capable of assuming the entire load current before the output voltage decreases more than ? v max . this places an upper limit on inductance. equation 31 gives the upper limit on l for the cases when the trailing edge of the current transient causes a greater output-voltage deviation than the leading edge. equation 32 addresses the leading edge. normally, the trailing edge dictates the selection of l because duty cycles are usually less than 50%. nevertheless, both inequalities should be evaluated, and l should be se lected based on the lower of the two results. in each equation, l is the per-channel inductance, c is the total output capacitance, and n is the number of active channels. 0 f p1 f z2 open loop e/a gain f z1 f p2 f lc f ce compensation gain gain frequency modulator gain figure 23. asymptotic bode plot of converter gain closed loop gain 20 d max v ? in v osc --------------------------------- log 20 r2 r1 ------- - ?? ?? log log log f 0 g mod g fb g cl ? v esl () di dt ---- - ? esr ()? i ? + (eq. 29) l esr () v in nv ? out ? ?? ?? v out ? f sw v in v pp max () ?? ------------------------------------------------------------------- - (eq. 30) l 2ncv o ??? ? i () 2 --------------------------------- ? v max ? iesr ? () ? ? (eq. 31) l 1.25 () nc ?? ? i () 2 --------------------------------- - ? v max ? i esr ? () ? v in v o ? ?? ?? ?? (eq. 32) isl8102
24 fn9247.0 october 19, 2005 switching frequency there are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper mosfet loss calculation. these effects are outlined in mosfets , and they establish the upper limit for the switching frequency. the lowe r limit is established by the requirement for fast transie nt response and small output- voltage ripple as outlined in output filter design . choose the lowest switching frequency that allows the regulator to meet the transient-response requirements. switching frequency is determined by the selection of the frequency-setting resistor, r fs . figure 24 and equation 33 are provided to assist in selecting the correct value for r fs . input capacitor selection the input capacitors are responsible for sourcing the ac component of the input current flowing into the upper mosfets. their rms current capa city must be sufficient to handle the ac component of t he current drawn by the upper mosfets which is related to duty cycle and the number of active phases. for a two-phase design, use figure 25 to determine the input-capacitor rms current requirement set by the duty cycle, maximum sustained output current (i o ), and the ratio of the peak-to-peak inductor current (i l,pp ) to i o . select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the rms current calculated. the voltage rating of the capacitors should also be at least 1.25 times greater than the maximum input voltage. figure 26 provides the same input rms current information for single-phase designs. use the same approach for selecting the bulk capacitor type and number. low esl, high-frequency ceramic capacitors are needed in addition to the input bulk capacitors to suppress leading and falling edge voltage spikes. the spikes result from the high current slew rate produced by the upper mosfet turn on and off. place them as close as possible to each upper mosfet drain to minimize board parasitics and maximize suppression. layout considerations mosfets switch very fast and efficiently. the speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, radiate noise into the circuit and lead to device overvoltage stress. careful component layout and printed circuit design minimizes the voltage spikes in the converter. consider, as an example, the turnoff transition of the upper pwm mosfet. prior to turnoff, the upper mosfet was carrying channel current. during the turnoff, current stops flowing in the upper mosfet and is picked up by the lower mosfet. any inductance in the r fs 10 10.61 1.035 f sw () log ? ? [] = (eq. 33) figure 24. r fs vs switching frequency 100k 200k 500k 1m 2m switching frequency (hz) r fs value (k ? ) 10 20 50 100 200 figure 25. normalized input-capacitor rms current for 2-phase converter 0.3 0.1 0 0.2 input-capacitor current (i rms/ i o ) 00.4 1.0 0.2 0.6 0.8 duty cycle (v in/ v o ) i l,pp = 0 i l,pp = 0.5 i o i l,pp = 0.75 i o figure 26. normalized input-capacitor rms current for single-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v in /v o ) input-capacitor current (i rms /i o ) 0.6 0.2 0 0.4 i l,pp = 0 i l,pp = 0.5 i o i l,pp = 0.75 i o isl8102
25 fn9247.0 october 19, 2005 switched current path generates a large voltage spike during the switching interval. carefu l component selection, tight layout of the critical compone nts, and short, wide circuit traces minimize the magnitude of voltage spikes. there are two sets of crit ical components in a dc/dc converter using a isl8102 controller. the power- components are the most critical because they switch large amounts of energy. next are small signal components that connect to sensitive nodes or supply critical bypassing current and signal coupling. it is important to have a symmet rical layout, preferably with the controller equidistantly locat ed from the two power trains it controls. equally important ar e the gate drive lines (ugate, lgate, phase): since they dr ive the power train mosfets using short, high current pulses, it is important to size them as large and as short as possibl e to reduce their overall impedance and inductance. extra ca re should be given to the lgate traces in particular since keeping the impedance and inductance of these traces helps to significantly reduce the possibility of shoot-through. equidistant placement of the controller to the two power trains also helps keeping these traces equally short (equal im pedances, resulting in similar driving of both sets of mosfets). the power components should be placed first. locate the input capacitors close to the power switches. minimize the length of the connections between the input capacitors, c in , and the power switches. locate the output inductors and output capacitors between the mosfets and the load. locate the high-frequency decoupling capacitors (ceramic) as close as practicable to the decoupling tar get, making use of the shortest connection paths to any internal planes, such as vias to gnd immediately next, or even onto the capacitor solder pad. the critical small components include the bypass capacitors for vcc and pvcc. locate th e bypass capacitors, cbp, close to the device. it is especially important to locate the components associated with the feedback circuit close to their respective controller pins, since they belong to a high- impedance circuit loop, sensitiv e to emi pick-up. it is also important to place current sense components close to their respective pins on the isl8102, including the risen resistors, rs, rcomp, ccomp. for proper current sharing route two separate symmetrical as possible traces from the corresponding phase node for each risen. a multi-layer printed circuit board is recommended. figure 27 shows the connections of the critical components for the converter. note that capacitors c xxin and c xxout could each represent numerous physical ca pacitors. dedica te one solid layer, usually the one underneath the component side of the board, for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. keep the metal runs from the phase terminal to inductor l out short. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase nodes. use the remainin g printed circuit layers for small signal wiring. the wiring traces from the ic to the mosfets? gates and sources should be sized to carry at least one ampere of current (0.02? to 0.05?). isl8102
26 fn9247.0 october 19, 2005 via connection to ground plane island on power plane layer island on circuit plane layer key figure 27. printed circuit board power planes and islands heavy trace on circuit plane layer +12v +12v load c boot1 r isen1 r isen2 c boot2 c bin1 (c hfout ) c bout c hf1 c bin2 locate close to ic locate near load; (minimize connection path) locate near switching transistors; (minimize connection path) (minimize connection path) c hf2 c comp r comp r s r s r ocset pgood vdiff fb comp vcc isen1 isl8102 ref1 fs ofst ref phase1 ugate1 boot1 lgate1 isen2 phase2 ugate2 boot2 lgate2 isum icomp iref vsen rgnd ocset ref0 +5v pvcc enll +12v gnd ovp 2ph dac droop c 1 r 2 c 2 r 1 c hf0 r ofst r ref c ref c sum to pvcc c hf01 l out1 l out2 r fs isl8102
27 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9247.0 october 19, 2005 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l32.5x5 32lead quad flat no-lead plastic package (compliant to jedec mo-220vhhd-2 issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.18 0.23 0.30 5, 8 d 5.00 bsc - d1 4.75 bsc 9 d2 2.95 3.10 3.25 7, 8 e 5.00 bsc - e1 4.75 bsc 9 e2 2.95 3.10 3.25 7, 8 e 0.50 bsc - k0.25 - - - l 0.30 0.40 0.50 8 l1 - - 0.15 10 n322 nd 8 3 ne 8 3 p- -0.609 --129 rev. 1 10/02 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm. isl8102

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